(1) Field of the Invention
The present invention relates to the fabrication methods used for semiconductor devices, and more specifically to a optimized process for creating the interconnecting contact stud, between the active device region and the overlying metallization.
(2) Description of Prior Art
The trend in the semiconductor industry has been to fabricate the smallest allowable devices, without sacrificing performance or reliability. By creating smaller devices, more chips per wafer will result, thus allowing a reduction in cost to be achieved. The trend to micro-miniaturazation, in terms of achieving sub-micron images for specific device elements, has largely occured as a result of advances in the photolithographic technology. The development of more sophisticated exposure cameras, as well as the development of more sensitive photoresist materials, have allowed sub-micron images in photoresist to be routinely obtained. In addition, similar advances in the dry etching discipline, has in turn allowed the sub-micron image in photoresist to be successfully transferred to an underlying semiconductor material, used for the fabrication of silicon devices. Advances in other fabrication sectors, such as ion implantation, (I/I), and low pressure chemical vapor deposition, (LPCVD), have also, contributed to the realization of semiconductor micro-miniaturazation.
Therefore although smaller specific device elements can be created via advances in semiconductor fabrication disciplines, usually resulting in performance, as well as cost improvements, these smaller elements can sometimes be more vulnerable to reliability concerns, then the larger dimensioned counterparts. For example, the interconnection between an active device element, in the semiconductor substrate, and an overlying metallization, is usually achieved via a metal stud or plug. The trend to sub-micron dimensions can result in a design in which the stud or plug has a much smaller cross-sectional area then the larger stud used for the less demanding, previous technology. However the current carrying capabilities for the smaller stud has not been relaxed, therefore resulting in increasing demands on the electromigration resistance properties of the stud material.
A specific material use for studs, and also, exhibiting outstanding electromigration resistance, is polycrystalline silicon. Applications using polysilicon as a stud, plug or contact material, have featured the creation of a contact hole to the active device region, followed by the deposition of polysilicon and the removal of polysilicon, from unwanted areas. The major problem with the polysilicon plug sequence has been the removal of the unwanted material. Several methods, for removal of unwanted polysilicon have been attempted. For example, reactive ion etching, (RIE), has the selectivity to remove polysilicon from the unwanted regions, over an insulator, without significantly attacking the underlying insulator. However the problem with the RIE solution is the continued removal of the polysilicon, in the contact hole, during the overetch section of the RIE procedure. Another solution for the removal of unwanted polysilicon material is a chemical-mechanical polishing, (CMP), process, described by Boyd, et al, in U.S. Pat. No. 5,316,978. The CMP process offers excellent selectivity, and also does not result in a significant removal of polysilicon in the contact hole. However CMP processing adds complexity, as well as cost to the device fabrication sequence. The invention now detailed will show a simple procedure for removing unwanted material from the underlying dielectric, while leaving the desired stud material, unattacked in the contact area.